Optimization of Domino Logic in Terms of Power Dissipation and Delay for High Speed Applications using CMOS
Propagation delay and power dissipation is the measure concern in designing of a VLSI circuit at 90nm or 45nm technology. For high performance circuit designing with ability of high speed with low power dissipation the existing technology is modify using an extra NMOS circuit in the existing technology for decreasing the power and delay of the circuit. This research is done in term of de-creasing the power and delay of the domino logic circuit using EDA tanner tool. The modified domino logic circuit using CMOS tech-nology is design at s-edit and simulation is done at t-edit and w-edit for getting the result in form of delay, average power, EDP and PDP at various supply voltages from 1v to 0.5v.